Low-Voltage Integrated Circuits Design and Application

One of the most challenging tasks for analog and digital designers is to maintain the circuit performances by developing novel circuit structures, robust, reliable, and capable of operating with low supply voltage.
In recent years, the design of low voltage and ultra-low power circuits is, indeed, of paramount importance. This is motivated by the power constraints and the advanced deep submicron technologies that require lower and lower supply voltages, less than 1 V. Even lower supply voltage may be requested for low-power systems, especially the ones applied in biomedical implantable or wearable electronic devices, autonomous sensor nodes supplied with non-conventional energy sources, the Internet of Things networks, and other similar applications.
This Special Issue consists of twenty-one papers covering a broad range of topics related to the design and applications of low voltage integrated circuits, from analog amplifiers, memories, analog to digital converters, oscillators, transceivers, charge pumps, circuits for signal processing, and beyond.
As the first cluster of applications related to the low voltage “challenge,” we can find several circuits dedicated to drive memories and communication circuits. For example, in [1,2], novel back-bias voltage (VBB) generators are proposed to overcome the increasing difficulties in sensing cell data in low-power DRAM. In [3], a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The proposed protocol aims to use fewer wires for the interface, reducing the complexity and the area of the chip design. In [4], a method is proposed to increase the read margin in 8T SRAM at lower voltage operation. Traditional 6T SRAM exhibits poor stability with voltage scaling: therefore, in [5], a novel 8T static RAM for reliable subthreshold operation is proposed employing a fully differential scheme.
Low voltage supply has a particularly detrimental effect on the performances of analog circuits. Several works have been devoted to novel circuital schemes to overcome this problem. Analog amplifiers are probably the most important building block in signal processing, and therefore, special attention is devoted to understanding the most critical issues and to propose novel schemes. For example, in [6], a three-stage CMOS amplifier is depicted, which can drive a very large capacitive load. In [7], the susceptibility to Electromagnetic Interference is deeply investigated, and different topologies suited for low voltage supply are compared.
One of the most interesting application fields of ultra-low-power amplifiers is biomedical signal conditioning. In [8], a novel general-purpose biomedical amplifier is proposed, based on flipped voltage follower.
Among the proposed circuital scheme to overcome the detrimental effect of low voltage in analog amplifiers, the most radical approach is probably to implement analog functions through digital blocks, as suggested in References [9,10]. Additionally, in [11], a fast transient digital LDO is proposed and in Reference [12] a time-to-digital converter based on an all-digital voltage controlled oscillator is depicted.
DC/DC converters and power management are an important task in low voltage systems. In [13], regulated charge pumps are compared using Verilog-AMS. In [14], a methodology to early estimate the power consumption of digital circuits is proposed. Analog to digital converters are another important building block. In [15], a power-efficient pipelined ADC is proposed. Digital blocks for communications, interfaces, and interconnections are investigated in Reference [16,17,18]. In [16], a high-speed full-duplex transceiver in 28 nm CMOS technology is proposed. In [17], a low power aviation microsystem is discussed: the proposed chip has the advantage of small size and ultra-low power consumption compared to the traditional PCB circuit design. The work presented in Reference [18] faces the difficulties and challenges of scalable I/Os. In [19], an analog lock-in amplifier with extremely low power consumption is proposed; it is fabricated in a standard 180 nm CMOS process. A convolutional neural network is, instead, the topic of Reference [20].
Finally, in [21], fast and accurate work on new materials is presented: in particular, the results show that by replacing the SiO2 dielectric mediums with the nanoglass, the maximum reduction of delay time and peak noise voltage is 25.202 ns and 0.102 V for an interconnect length of 3000 µm. The results presented in this paper would be useful to aid in the enhancement of performance of on-chip interconnects and provide guidelines for signal characteristic analysis of interconnection.
From the published papers, which cover an extremely wide area of low voltage, low power integrated circuits, and pleasant reading experience, many ideas could be inspired. This is both in designing novel schematics that can overcome low voltage design problems and in thinking of new technology solutions and new materials, which can face future ICs.